Copper pillar to be mainstream FC packaging technology in 2012

1. [verwijderd] 5 juni 2011 12:44

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   [Friday 3 June 2011]
   
   IC packagers Advanced Semiconductor Engineering (ASE), Amkor Technology, Siliconware Precision Industries (SPIL) and STATS ChipPAC have all started developing a new flip-chip (FC) packaging technology dubbed copper pillar bumping, according to industry sources. The new packaging method will replace conventional solder bumping as the mainstream technology in 2012.
   
   The transition to a new FC packaging technology is being sped up by growing demand for smaller form factors and low cost products such as smartphones, the sources indicated. Meanwhile, further advances in shrinking process geometries are also required to produce chips with high level of integration and low power consumption. While migrating to smaller-geometry processes, reducing manufacturing costs has become more fundamental for chip companies, the sources pointed out.
   
   Major developers of communications-related chips including Broadcom, Infineon Technologies, Marvell Technology, Qualcomm and Texas Instrument (TI) have all adopted copper pillar in their chip devices built using 28nm process technology, the sources also learned. Amkor, for instance, has partnered with TI to use the new chip-packaging technology for devices at the 4Xnm node and below.
   
   Copper pillar has already been applied to PC-related chips. Intel uses the technology for some of its flip-chip product lines.
   
   ASE recently began sampling its copper pillar bumping technology to customers, which are gearing up for migration to 28nm process production, the sources said. ASE is expected to significantly ramp up production on copper pillar bond processing in 2012, the sources believe.
   
   For other Taiwan-based packaging and testing firms including Chipbond Technology, the huge capex needed to invest in new production lines for copper pillar bumping remains a concern, the sources indicated. Building a copper pillar production line capable of producing 10,000 12-inch wafers requires NT$1-2 billion (US$35-70 million), the sources estimated.
   
   
2. [verwijderd] 5 juni 2011 13:10

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   Beeldscherm.
   Het is goed dat je de ontwikkelingen in de gaten houdt.Ik ben niet zo technisch onderlegd dat ik het precies op waarde weet te schatten.Maar hoe zit Besi in dit proces?Doen zij daar wel mee met de ontwikkelingen?
3. [verwijderd] 6 juni 2011 15:23

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   Flip Chip is a chip interconnect technology introduced
   by IBM already in the early `60s. Since it
   allows spreading the electrical connections over the
   whole chip area, it was traditionally used for high
   I/O devices, e.g. microprocessors, graphic processors
   and network switching circuits. Matching the
   high-end performance requirements that typically
   go hand in hand with high I/O count, flip chip offers
   the best electrical path (low resistance, capacitance
   and inductance) between chip and package. These
   mechanical and electrical properties of flip chip
   interconnects explain why we see such tremendous
   growth in flip chip on leadframe (FCOL ) packages.
   Portable Devices at Low Cost
   Battery-powered portable electronics such as Apple’s
   iPhone and iPad require smaller devices that don’t
   waste precious electrical energy. Flip chip packages
   offer exactly this: maximum die size in small packages
   (see Fig. 2) and excellent current conductivity.
   No wonder that more and more power management
   ICs (e.g. voltage regulators and converters) are
   offered in FCOL packages. Leadframe designs like
   high density QFN and SOT are replacing more expensive
   laminate substrates. The number of I/Os in
   these packages is typically very low, most often
   < 10. This allows very short flux dipping times so
   that the throughput (fluxing is in the critical path
   of a flip chip bonder) is high. The bumps connecting
   the chip surface to the metal leadframe are built
   in so called copper pillar technology; where a tiny
   amount of solder sits on top of a copper cylinder
   (see Fig. 1). It took some time to build up the necessary
   infrastructure, but now a lot of Cu bumping
   capacity is available at low cost. Further downstream,
   process cost came down using molded
   underfill in QFN matrix leadframes, eliminating the
   capillary underfill dispensing step. The only
   “missing link” was the proper mass production
   flip chip bonder.
   Mass Production Flip Chip Subcontract Assembly
   The semiconductor assembly, packaging and testing
   services (SATS) companies, typically located in Asia,
   have specific needs for their production equipment.
   They need best cost of ownership (CoO), which not
   only means high throughput and low investment
   cost. Equipment should be easy to set up and run,
   
   www.meco.nl/upload/Besi_Spotlights_11...
4. [verwijderd] 6 juni 2011 15:58

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   www.i-micronews.com/upload/Interviews...
5. [verwijderd] 3 juli 2012 14:23

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   nog maar eens onder de aandacht brengen want ook in 2012 gaat dit proces door,ook bij klanten van Besi,
   
   Greatek to expand capacity
   
   ....In view of the trend of rising gold prices, Greatek has been replacing gold bumping packaging with copper-wire bonding process and has initially applied copper-wire bonding to QFP (quad flat package), the company indicated. As a result, the proportion of wire bonding revenues for copper-wire bonding rose to 30% in the first quarter of 2012 and will keep going up, Greatek said.
   
   www.laosonline.net/component/k2/item/...
   
   nu weet ik niet of Lingsen klant is maar Greatek wel...
6. [verwijderd] 3 juli 2012 14:37

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   quote:

   beeldscherm schreef:

   nog maar eens onder de aandacht brengen want ook in 2012 gaat dit proces door,ook bij klanten van Besi,
   
   Greatek to expand capacity
   
   ....In view of the trend of rising gold prices, Greatek has been replacing gold bumping packaging with copper-wire bonding process and has initially applied copper-wire bonding to QFP (quad flat package), the company indicated. As a result, the proportion of wire bonding revenues for copper-wire bonding rose to 30% in the first quarter of 2012 and will keep going up, Greatek said.
   
   www.laosonline.net/component/k2/item/...
   
   nu weet ik niet of Lingsen klant is maar Greatek wel...
   

   ps,wat blijven we eigenlijk achter op ASML/ASMI we hebben nog wat in te halen of speelt er iets...
7. [verwijderd] 3 juli 2012 14:41

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   Texas Instruments Drives Adoption of Copper Wire Bonding Technology, Delivering Nearly 6.5 Billion Units to Customers
   
   June 6, 2012
   Texas Instruments Incorporated (NASDAQ: TXN) (TI) announced it has shipped nearly 6.5 billion units of copper wire bonding technology in its analog, embedded processing and wireless products. This milestone underscores TI's confidence in copper as a viable replacement to gold in its semiconductor product roadmaps, and the electronics industry's acceptance of the technology, due to performance, quality and reliability benefits for a range of applications.
   
   
8. [verwijderd] 3 juli 2012 14:56

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   STATS ChipPAC’s Copper Wirebond Shipments Exceed One Billion Units
   Proven manufacturing capabilities combined with advanced packaging technology accelerates growth in copper wirebond
   
   Singapore – 19/06/2012 –
   
   STATS ChipPAC Ltd. (“STATS ChipPAC” or the “Company” – SGX-ST: STATSChP), a leading semiconductor test and advanced packaging service provider, today announced that it has reached the production milestone of one billion copper wirebond units shipped. This achievement was driven by the Company’s proven high volume manufacturing capabilities combined with STATS ChipPAC’s engineering focus on copper wire technology development for a broad range of advanced, multi-die laminate and leaded packages including three dimensional (3D) packaging.
   
   “We have reached a number of technology and manufacturing achievements in our copper wire packaging roadmap that have enabled us to serve the needs of our diverse customer base and support the acceleration of our copper wire program as more and more customers experience the benefits and reliability of copper wire interconnect as an alternative to gold. Today, we are actively qualifying and ramping to production a wide range of advanced multi-die laminate and leaded packages as well as thermally enhanced mold compounds compatible with copper wire to further increase thermal performance. We are in volume production with copper wirebond devices down to the 40 nanometer (nm) silicon wafer node and are qualified on the 28nm wafer node,” said Wan Choong Hoe, Executive Vice President and Chief Operating Officer, STATS ChipPAC.
   
   Copper wire provides better conductivity than gold, improved electrical and thermal performance, and stronger mechanical properties. With the semiconductor industry trend moving towards higher pin counts, finer bond pad pitches and thinner wire diameters, there is a growing demand to utilize copper wire in more advanced multi-die laminate and leaded packages including three dimensional (3D) packaging. STATS ChipPAC’s copper wire offering is rapidly expanding with wire diameters down to 0.6 mils and a broad technology offering including die-to-die bonding and a range of 3D package configurations including stacked die, side-by-side die and a combination of stacked plus side-by-side die packages.
   
   
9. [verwijderd] 3 juli 2012 15:15

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   Signetics to buy semiconductor equipment from Disco, TSK, Shinkawa, Esec and K&S to expand capacity
   2012-06-19 16:32:56, India
   
   Telecom Lead America: Signetics has decided to buy additional semiconductor assembly process equipment from Disco, TSK, Shinkawa, Esec and K&S to expand their capacity.
   
   This project will enable Signetics to grow its market share in the assembly and test of products for mobile consumer applications.
   
   ...To increase Signetics' capacity at the die attach process, new Shinkawa and Esec die attach equipment will be added.
   
   
10. [verwijderd] 3 juli 2012 15:59

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    SPIL to expand packaging, testing capacity at China subsidiary
    28 May '12,
    
    SPIL to expand packaging, testing capacity at China subsidiary
    SPIL to expand packaging, testing capacity at China subsidiary Mavis Hong, Taipei; Adam Hwang, DIGITIMES [Monday 28 May 2012] Siliconware Precision Industries (SPIL), a Taiwan-based provider of IC packaging/testing service, will add investment of US$100 million in Siliconware Technology (Suzhou) to expand the China subsidiary's copper-wire bonding capacity, according to SPIL. The capacity expansion targets ICs for entry- and mid-level communication, PC and consumer electronics from China-based IC design houses, SPIL indicated. Currently, China-based IC designers take up more than 80% of Siliconware Technology's clients, SPIL noted. Siliconware Technology had 1,165 wire bonders, including for QFN (quad-flat no lead) and CSP (chip scale package) packaging, and 62 sets of testing equipment as of first-quarter 2012, SPIL said
    
    ..dit is leuk,US$100 million om uit te breiden in copper-wire bonding capaciteit....
11. vdMandele 3 juli 2012 16:30

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    ksnap er geen flikker van. gaan ze nou kopen van besi, kopen van de concurrent, of gaan ze zelf hetzelfde doen wat besi doet?!?
12. [verwijderd] 3 juli 2012 16:38

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    quote:

    vdMandele schreef:

    ksnap er geen flikker van. gaan ze nou kopen van besi, kopen van de concurrent, of gaan ze zelf hetzelfde doen wat besi doet?!?
    

    1 ze zijn klant
    2 ze verkopen goed "spul"
    3 klanten zijn tevreden prijs/services etc
    4 Waarom zou je dan ergens anders "inkopen"
    5 dus zou zomaar kunnen..kassa Besi
13. [verwijderd] 4 juli 2012 19:27

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    Friday, 04 May 2012 00:02
    ASE to issue overseas convertible bonds worth NT$9 billion
    
    ...ASE has set a capex target of US$800 million for 2012. The majority of the capex will be allocated to expand capacity for copper wire-bonding processes, and also capacity for bumping and other wafer-level packaging solutions.
    
    Of ASE's 2012 capex, US$400 million will be used for copper wire-bonding capacity. The copper segment is expected to account for 53% of ASE's total wire bonding revenues in the second quarter of 2012, the firm said previously.
    
    www.laosonline.net/component/k2/item/...
    
    Packaging and testing house Advanced Semiconductor Engineering (ASE) will expand 2012 capital expenditure (capex) from US$700-750 million originally to US$800 million mainly due to expected increases in orders from IDMs, company CFO Joseph Tung told at an April 27 investors conference.
    
    The hiked capex will consist of US$400 million for copper wire-bonding capacity, US$200 million for bumping and flip chip capacity and US$200 million for testing capacity, Tung indicated.
    
    With capex of US$156 million for the first quarter, ASE plans to spend more than US$300 million in the second quarter, Tung said.
    
    ASE's utilization for bumping and wire-bonding stood at nearly 100% and 75% respectively in the first quarter of 2012 and the company expects both segments to reach fully utilization in the second quarter, Tung indicated.
    
    
14. [verwijderd] 5 juli 2012 11:19

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    Geachte beeldscherm forum lid
    
    Begint me behoorlijk te duizelen ..ik ben geen moderator maar..
    
    Iedereen is daar uiteraard vrij in
    
    ..In een forum is het van belang deze niet te 'overspoelen' met copy/paste informatie,maar gericht in te gaan op Besi met andere forum leden,en een mening te delen
    
    
    
    Natuurlijk is alle informatie die betrekking heeft op Besi welkom, maar om nu een compleet algemeen databank file aan te gaan leggen ..meer eventueel verwijzen naar, houdt het overzichtelijk
    
    
    
    met vriendelijke groet,
    
    
    
    Totoo
    
    
15. [verwijderd] 7 juli 2012 13:46

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    Ik vind de diverse berichten van beeldscherm wel handig. Ze geven een beeld van wat er in de wereld van semiconductors in het algemeen en klanten van Besi in het bijzonder speelt. De teneur is investeringen nemen toe en bezettingsgraden tenderen naar 100%. De cijfers van het 2-de kwartaal zullen erg goed moeten zijn evenals de outlook. Zijn cijfers en outlook 'wel aardig', dan is de vraag of Besi het t.o.v. de markt wel zo goed doet.
16. [verwijderd] 28 november 2013 15:12

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    Could copper pillar change the ecosystem ?
    
    The future of bumping is copper, and that could change everything. Though originally
    developed at the IDMs, players from foundries to OSATs are now developing a variety
    of differing copper pillar and micro-bumping solutions for a range of customers,
    looking re-designing the substrate, weighing extending refl ow vs scaling thermal
    compression bonding, and developing probe and test systems.
    
    www.i-micronews.com/upload/pdf/3DPack...
17. [verwijderd] 28 november 2013 17:30

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    quote:

    totoo schreef op 5 juli 2012 11:19:

    Geachte beeldscherm forum lid
    
    Begint me behoorlijk te duizelen ..ik ben geen moderator maar..
    
    Iedereen is daar uiteraard vrij in
    
    ..In een forum is het van belang deze niet te 'overspoelen' met copy/paste informatie,maar gericht in te gaan op Besi met andere forum leden,en een mening te delen
    
    
    
    Natuurlijk is alle informatie die betrekking heeft op Besi welkom, maar om nu een compleet algemeen databank file aan te gaan leggen ..meer eventueel verwijzen naar, houdt het overzichtelijk
    
    
    
    met vriendelijke groet,
    
    
    
    Totoo
    
    Besi is zelf niet zo scheutig met informatie.En dan druk ik mij voorzichtig uit.Ik waardeer het zeer als forumleden informatie aandragen dat direct of indirect te maken heeft met Besi. Keep on beeldscherm with the good work .